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| SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1805 Advance Information 132 x 68 STN LCD Segment / Common Monochrome Driver with Controller This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1805 Series Rev 1.1 P 1/52 Jun 2004 Copyright 2004 Solomon Systech Limited TABLE OF CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GENERAL DESCRIPTION....................................................................................................................... 5 FEATURES............................................................................................................................................... 5 ORDERING INFORMATION .................................................................................................................... 5 BLOCK DIAGRAM ................................................................................................................................... 6 DIE PAD FLOOR PLAN........................................................................................................................... 7 PIN DESCRIPTION ................................................................................................................................ 11 FUNCTIONAL BLOCK DESCRIPTIONS .............................................................................................. 16 COMMAND TABLE................................................................................................................................ 24 COMMAND DESCRIPTIONS................................................................................................................. 28 MAXIMUM RATINGS ............................................................................................................................. 36 DC CHARACTERISTICS ....................................................................................................................... 37 AC CHARACTERISTICS ....................................................................................................................... 39 APPLICATION EXAMPLES................................................................................................................... 46 PACKAGE INFORMATION ................................................................................................................... 49 Solomon Systech Jun 2004 P 2/52 Rev 1.1 SSD1805 Series TABLE OF TABLES Table 1 - Ordering Information ............................................................................................................................ 5 Table 2 - SSD1805 Series Bump Die Pad Coordinates (Bump center) .............................................................. 8 Table 3 - Arrangement of common at different multiplex modes ...................................................................... 15 Table 4 - Data Bus selection Modes.................................................................................................................. 17 Table 5 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 18h................. 18 Table 6 - Gain Setting........................................................................................................................................ 20 Table 7 - Temperature compensation coefficient .............................................................................................. 20 Table 8 - Command Table ................................................................................................................................. 24 Table 9 - Extended Command Table................................................................................................................. 26 Table 10 - Read Command Table ..................................................................................................................... 27 Table 11 - Automatic Address Increment .......................................................................................................... 28 Table 12 - ROW pin assignment for COM signals for SSD1805 in an 68 MUX display ................................... 35 Table 13 - Maximum Ratings............................................................................................................................. 36 Table 14 - DC Characteristics ........................................................................................................................... 37 Table 15 - AC Characteristics............................................................................................................................ 39 Table 16 - Parallel 6800-series Interface Timing Characteristics...................................................................... 40 Table 17 - Parallel 6800-series Interface Timing Characteristics...................................................................... 41 Table 18 - Parallel 8080-series Interface Timing Characteristics...................................................................... 42 Table 19 - Parallel 8080-series Interface Timing Characteristics...................................................................... 43 Table 20 - 4-wires Serial Interface Timing Characteristics................................................................................ 44 Table 21 - 4-wires Serial Interface Timing Characteristics................................................................................ 45 SSD1805 Series Rev 1.1 P 3/52 Jun 2004 Solomon Systech TABLE OF FIGURES Figure 1 - SSD1805 Block Diagram.....................................................................................................................................6 Figure 2 - SSD1805 Die Pad Floor Plan ...............................................................................................................................7 Figure 3 - Display Data Read with the insertion of dummy read .......................................................................................16 Figure 4 - SSD1805 Hardware configuration .....................................................................................................................19 Figure 5 - Contrast curve ....................................................................................................................................................21 Figure 6 - TC 0 oscillator typical frame frequency with variation in temperature..............................................................22 Figure 7 - LCD Driving Waveform ....................................................................................................................................23 Figure 8 - Contrast Control Flow........................................................................................................................................29 Figure 9 - OTP programming circuitry ...............................................................................................................................31 Figure 10 - Flow chart of OTP programming Procedure....................................................................................................32 Figure 11 - Parallel 6800-series Interface Timing Characteristics (P/S = H, C68/80 = H).................................................40 Figure 12 - Parallel 6800-series Interface Timing Characteristics (P/S = H, C68/80 = H).................................................41 Figure 13 - Parallel 8080-series Interface Timing Characteristics (P/S = H, C68/80 = L) .................................................42 Figure 14 - Parallel 8080-series Interface Timing Characteristics (P/S = H, C68/80 = L) .................................................43 Figure 15 - 4-wires Serial Interface Timing Characteristics (P/S = L, C68/80 = L)...........................................................44 Figure 16 - 4-wires Serial Interface Timing Characteristics (P/S = L, C68/80 = L)...........................................................45 Figure 17 - Application Example I (4-wires SPI mode) .....................................................................................................46 Figure 18 - Application Example II (6800 PPI mode)........................................................................................................47 Figure 19 - Applications notes for VDD/VDDIO connection..................................................................................................48 Figure 20 - SSD1805TR1 TAB Drawing (Copper view) ...................................................................................................50 Figure 21 - SSD1805TR1 TAB Drawing (Detail view & pin assignment) ........................................................................51 Solomon Systech Jun 2004 P 4/52 Rev 1.1 SSD1805 Series 1 General Description SSD1805 is a single-chip CMOS LCD driver with controller for dot-matrix graphic liquid crystal display system. SSD1805 consists of 200 high-voltage driving output pins for driving maximum 132 Segments, 68 Commons / 132 Segments, 64 Commons and 1 icon-driving Common / 132 Segments, 54 Commons and 1 icon-driving Common / 132 Segments, 32 Commons and 1 icon-driving Common. SSD1805 can also be switched among 32, 54, 64 or 68 display multiplex ratios by hardware pin selection. SSD1805 consists of 132 x 68 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from common MCU through 8-bit 6800-series / 8080-series compatible Parallel Interface or 4-wires Serial Peripheral Interface by software program selections. SSD1805 embeds DC-DC Converter, On-Chip Oscillator and Bias Divider to reduce the number of external components. With the advance design, low power consumption, stable LCD operating voltage and flexible die package layout, SSD1805 is suitable for any portable battery-driven applications requiring long operation period with compact size. 2 FEATURES * * * * Power Supply: VDD = 1.8V - 3.6V VDDIO = 1.8V - 3.6V VCI = 1.8V - 3.6V LCD Driving Output Voltage: VLCD = +12.5V Low Current Sleep Mode Pin selectable 68/64/54/32 multiplex ratio configuration. Maximum display size: o 132 columns by 68 rows o 132 columns by 64 rows with one icon line o 132 columns by 54 rows with one icon line o 132 columns by 32 rows with one icon line 8-bit 6800-series / 8080-series Parallel Interface, 4-wires Serial Peripheral Interface On-Chip 132 X 68 = 8976 bits Graphic Display Data RAM Column Re-mapping and RAM Page scan direction control Vertical Scrolling by Common On-Chip Voltage Generator or External LCD Driving Power Supply Selectable Pin selectable 2X/3X/4X/5X On-Chip DC-DC Converter with internal flying capacitors. 64 Levels Internal Contrast Control Programmable LCD Driving Voltage Temperature Compensation Coefficients On-Chip Bias Divider with internal compensation capacitors (except VOUT) Programmable multiplex ratio: 1/9 to 1/68 Programmable bias ratio: 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 Display Offset Control Non-Volatile Memory (OTP) for calibration * * * * * * * * * * * * * 3 ORDERING INFORMATION Ordering Part Number SSD1805Z SSD1805TR1 SEG 132 132 COM 64/54/32 + 1 icon or 68 64 + 1 icon Package Form Gold Bump Die TAB Reference Figure 2 on Page 7 Figure 20 on page 50 Remark - Table 1 - Ordering Information SSD1805 Series Rev 1.1 P 5/52 Jun 2004 Solomon Systech 4 BLOCK DIAGRAM ICONS ROW0 ~ ROW67 SEG0 ~ SEG131 HV Buffer Cell Level Shifter Level Selector Display Data Latch MSTAT M /DOF M/ S Display Timing Generator CL CLS C0 C1 Oscillator LCD Driving Voltage Generator 2X/3X/4X/5X Regulated DC/DC Converter, Contrast Control, Bias Divider, Temperature Compensation VF VCI IRS VOUT B0 B1 VLREF VHREF VFS TEST0 GDDRAM 132 x 68 bits VDD TEST22 Command Decoder VDDIO VSS VSS1 Command Interface Parallel/Serial Interface RES P/ S CS 1 CS2 D/ C E( RD ) C68/( 80 ) R/W ( WR ) D7 D6 D5 D4 D3 D2 D1 D0 (SDA) (SCK) Figure 1 - SSD1805 Block Diagram Solomon Systech Jun 2004 P 6/52 Rev 1.1 SSD1805 Series 5 DIE PAD FLOOR PLAN Note: 1. Diagram showing the die face up. 2. Coordinates are reference to center of the chip. 3. Unit of coordinates and Size of all alignment marks are in um. 4. All alignment keys do not contain gold bump. NC ROW22 ROW23 ROW24 : : : : : : : : : : : : : : : : : : : : : : : : : : ROW31 ROW32 ROW33 NC NC ROW21 ROW20 ROW19 : : : : : : : : : : : : : : : : : : : : : : : : : : ROW2 ROW1 ROW0 SEG0 SEG1 SEG2 : : : : : : : : ; ; ; ; ; ; ; ; ; : : : : : : : : : : : : : : : ; ; : ; ; : : : ; ; ; ; ; ; ; ; ; ; ; ; ; : : : ; ; ; ; ; ; : : : : SEG129 SEG130 SEG131 ROW34 ROW35 ROW36 : : : : : : : : : : : : : : : : : : : : : : : : : : : ROW53 ROW54 ROW55 NC NC TEST22 TEST21 TEST20 TEST19 TEST18 TEST17 TEST16 TEST15 TEST14 TEST13 TEST12 TEST11 TEST10 TEST9 TEST8 TEST7 TEST6 VDD B0 VSS B1 VDD C0 VSS C1 VDD IRS VSS /HPM VDD P/ S C68/( ) 80 Centre: 5103, -236 Centre: 5103,195 25 25 25 VSS CLS M/ S VDD VF VOUT TEST5 TEST4 TEST3 TEST2 TEST1 VDD VFS VFS VSS VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VHREF VHREF VCI VCI VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VLREF VLREF VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VDD VDD VDD VDD VDD VDD VDDIO VDDIO D7 (SDA) D6 (SCK) D5 D4 D3 D2 D1 D0 VDD E( RD ) R/W ( WR ) VSS D/ C 25 25 100 25 100 25 25 25 25 X 0,0 100 50 Centre: -5103, -236 Y 100 75 18 100 Centre: -5103, 195 100 RES VDD CS2 1 CS VSS /DOF CL M MSTAT TEST0 NC Die Size Die Thickness Typical Bump Height Bump Co-planarity (within die) 11.06 X 1.21 mm 53325 m 18 m <3 m 2 SSD1805 Series NC ROW67 ROW66 ROW65 : : : : : : : : : : : : : : : : : : : : : : : : : : : ROW58 ROW57 ROW56 NC PIN1 Figure 2 - SSD1805 Die Pad Floor Plan Rev 1.1 P 7/52 Jun 2004 Solomon Systech Table 2 - SSD1805 Series Bump Die Pad Coordinates (Bump center) Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal NC TEST0 MSTAT M CL /DOF VSS CS 1 CS2 VDD RES D/C VSS R / W ( WR ) E( RD ) VDD D0 D1 D2 D3 D4 D5 D6 (SCK) D7 (SDA) VDDIO VDDIO VDD VDD VDD VDD VDD VDD VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VLREF VLREF VSS VSS VSS X-pos -5167.10 -5035.80 -4959.50 -4883.20 -4806.90 -4730.60 -4654.30 -4578.00 -4501.70 -4425.40 -4349.10 -4272.80 -4196.50 -4120.20 -4043.90 -3967.60 -3891.30 -3815.00 -3738.70 -3662.40 -3586.10 -3509.80 -3433.50 -3357.20 -3280.90 -3204.60 -3128.30 -3052.00 -2975.70 -2899.40 -2823.10 -2746.80 -2670.50 -2594.20 -2517.90 -2441.60 -2365.30 -2289.00 -2212.70 -2136.40 -2060.10 -1983.80 -1907.50 -1831.20 -1754.90 -1678.60 -1602.30 -1526.00 -1449.70 -1373.40 Y-pos -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 Pad # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal VSS VSS VSS VSS VSS VSS VSS VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VCI VCI VHREF VHREF VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VSS VFS VFS VDD TEST1 TEST2 TEST3 TEST4 TEST5 VOUT VF VDD M/ S X-pos -1297.10 -1220.80 -1144.50 -1068.20 -991.90 -915.60 -839.30 -763.00 -686.70 -610.40 -534.10 -457.80 -381.50 -305.20 -228.90 -152.60 -76.30 0.00 76.30 152.60 228.90 305.20 381.50 457.80 534.10 610.40 686.70 763.00 839.30 915.60 991.90 1068.20 1144.50 1220.80 1297.10 1373.40 1449.70 1526.00 1602.30 1678.60 1754.90 1831.20 1907.50 1983.80 2060.10 2136.40 2212.70 2289.00 2365.30 2441.60 Y-pos -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 Pad # Signal 101 CLS 102 VSS 103 C68/( 80 ) 104 P/ S 105 VDD 106 /HPM 107 VSS 108 IRS 109 VDD 110 C1 111 VSS 112 C0 113 VDD 114 B1 115 VSS 116 B0 117 VDD 118 TEST6 119 TEST7 120 TEST8 121 TEST9 122 TEST10 123 TEST11 124 TEST12 125 TEST13 126 TEST14 127 TEST15 128 TEST16 129 TEST17 130 TEST18 131 TEST19 132 TEST20 133 TEST21 134 TEST22 135 NC 136 NC 137 ROW33 138 ROW32 139 ROW31 140 ROW30 141 ROW29 142 ROW28 143 ROW27 144 ROW26 145 ROW25 146 ROW24 147 ROW23 148 ROW22 149 NC 150 NC X-pos 2517.90 2594.20 2670.50 2746.80 2823.10 2899.40 2975.70 3052.00 3128.30 3204.60 3280.90 3357.20 3433.50 3509.80 3586.10 3662.40 3738.70 3815.00 3891.30 3967.60 4043.90 4120.20 4196.50 4272.80 4349.10 4425.40 4501.70 4578.00 4654.30 4730.60 4806.90 4883.20 4959.50 5035.80 5167.10 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5372.00 5141.25 Y-pos -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -448.50 -376.00 -318.00 -260.00 -202.00 -144.00 -86.00 -28.00 30.00 88.00 146.00 204.00 262.00 320.00 378.00 448.50 Solomon Systech Jun 2004 P 8/52 Rev 1.1 SSD1805 Series Pad # 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Signal ROW21 ROW20 ROW19 ROW18 ROW17 ROW16 ROW15 ROW14 ROW13 ROW12 ROW11 ROW10 ROW9 ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 X-pos 5083.25 5025.25 4967.25 4909.25 4851.25 4793.25 4735.25 4677.25 4619.25 4561.25 4503.25 4445.25 4387.25 4329.25 4271.25 4213.25 4155.25 4097.25 4039.25 3981.25 3923.25 3865.25 3799.00 3741.00 3683.00 3625.00 3567.00 3509.00 3451.00 3393.00 3335.00 3277.00 3219.00 3161.00 3103.00 3045.00 2987.00 2929.00 2871.00 2813.00 2755.00 2697.00 2639.00 2581.00 2523.00 2465.00 2407.00 2349.00 2291.00 2233.00 Y-pos 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 Pad # 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Signal SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 X-pos 2175.00 2117.00 2059.00 2001.00 1943.00 1885.00 1827.00 1769.00 1711.00 1653.00 1595.00 1537.00 1479.00 1421.00 1363.00 1305.00 1247.00 1189.00 1131.00 1073.00 1015.00 957.00 899.00 841.00 783.00 725.00 667.00 609.00 551.00 493.00 435.00 377.00 319.00 261.00 203.00 145.00 87.00 29.00 -29.00 -87.00 -145.00 -203.00 -261.00 -319.00 -377.00 -435.00 -493.00 -551.00 -609.00 -667.00 Y-pos 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 Pad # 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Signal SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 X-pos -725.00 -783.00 -841.00 -899.00 -957.00 -1015.00 -1073.00 -1131.00 -1189.00 -1247.00 -1305.00 -1363.00 -1421.00 -1479.00 -1537.00 -1595.00 -1653.00 -1711.00 -1769.00 -1827.00 -1885.00 -1943.00 -2001.00 -2059.00 -2117.00 -2175.00 -2233.00 -2291.00 -2349.00 -2407.00 -2465.00 -2523.00 -2581.00 -2639.00 -2697.00 -2755.00 -2813.00 -2871.00 -2929.00 -2987.00 -3045.00 -3103.00 -3161.00 -3219.00 -3277.00 -3335.00 -3393.00 -3451.00 -3509.00 -3567.00 Y-pos 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 SSD1805 Series Rev 1.1 P 9/52 Jun 2004 Solomon Systech Pad # 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 Signal SEG128 SEG129 SEG130 SEG131 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 NC NC ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 ROW64 ROW65 ROW66 ROW67 NC X-pos -3625.00 -3683.00 -3741.00 -3799.00 -3865.25 -3923.25 -3981.25 -4039.25 -4097.25 -4155.25 -4213.25 -4271.25 -4329.25 -4387.25 -4445.25 -4503.25 -4561.25 -4619.25 -4677.25 -4735.25 -4793.25 -4851.25 -4909.25 -4967.25 -5025.25 -5083.25 -5141.25 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 -5372.00 Y-pos 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 448.50 378.00 320.00 262.00 204.00 146.00 88.00 30.00 -28.00 -86.00 -144.00 -202.00 -260.00 -318.00 -376.00 Bump Size PAD# Pad 1 Pad 2 - 134 Pad 135 Pad 136 - 149 Pad 150 - 327 Pad 328 - 341 X [um] 56 56 56 89 36 89 Y [um] 92 92 92 36 89 36 Pad pitch [um] (Min) 131.3 76.3 131.3 58 58 58 Pad pitch Y X Solomon Systech Jun 2004 P 10/52 Rev 1.1 SSD1805 Series 6 6.1 PIN DESCRIPTION MSTAT This pin is the static indicator driving output. The frame signal output pin, M, should be used as the back plane signal for the static indicator. The duration of overlapping could be programmable. See Extended Command Table for details. 6.2 M This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices while in slave mode, the pin receives frame signal from the master device. 6.3 CL This pin is the display clock input/output. In master mode with internal oscillator enabled (CLS pin pulled high), this pin supplies display clock signal to slave devices. In slave mode or when internal oscillator is disabled, the pin receives display clock signal from the master device or external clock source. 6.4 /DOF This pin is display blanking control between master and slave devices. In master mode, this pin supplies on/off signal to slave devices. In slave mode, this pin receives on/off signal from the master device. 6.5 CS 1, CS2 These pins are the chip select inputs. The chip is enabled for MCU communication only when both CS 1 is pulled low and CS2 is pulled high. 6.6 RES This pin is the reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse width for reset sequence is 20us. 6.7 D/ C This pin is Data/Command control pin. When the pin is pulled high, the data at D7 - D0 is treated as display data. When the pin is pulled low, the data at D7 - D0 will be transferred to the command register. R/W ( WR ) This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as Read/Write (R/W ) selection input. Read mode will be carried out when this pin is pulled high and write mode when low. When 8080 interface mode is selected, this pin is the Write ( WR ) control signal input. Data write operation is initiated when this pin is pulled low and the chip is selected. When serial interface mode is selected, this pin must be pulled low. 6.9 E( RD ) 6.8 This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the chip is selected. When 8080 interface mode is selected, this pin is the Read ( RD ) control signal input. Data read operation is initiated when this pin is pulled low and the chip is selected. When serial interface mode is selected, this pin must be pulled high. 6.10 D7 - D0 These pins are the 8-bit bi-directional data bus in parallel interface mode. D7 is the MSB while D0 is the LSB. When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK). SSD1805 Series Rev 1.1 P 11/52 Jun 2004 Solomon Systech 6.11 VDDIO This pin is the system power supply pin of bus IO buffer. Please refer to figure 19 on page 48 for connection example. 6.12 VDD This pin is the system power supply pin of the logic block. 6.13 VCI Reference voltage input for internal DC-DC converter. The voltage of generated VOUT equals to the multiple factor (2X, 3X, 4X or 5X) times VCI with respect to VSS1. Note: Voltage at this input pin must be larger than or equal to VDD. 6.14 VSS The VSS is the ground reference of the system. 6.15 VSS1 Reference voltage input for internal DC-DC converter. The voltage of generated VOUT equals to the multiple factor (2X, 3X, 4X or 5X) times VCI with respect to VSS1. Note: Voltage at this input pin must be equal to VSS. 6.16 VLREF This pin is the ground of internal operation amplifier. In normal power mode, it must connect to VSS. In low power mode, it must connect to VCI. Please refer to figure 19 on page 48 for the detail. 6.17 VHREF This pin is the power supply pin of the internal operation amplifier. It must connect to VOUT. 6.18 VOUT This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. If the internal DC-DC converter generates the voltage level at VOUT, the voltage level is used for internal referencing only. The voltage level at VOUT pin is not used for driving external circuitry. 6.19 VFS This is an input pin to provide an external voltage reference for the internal voltage regulator. The function of this pin is only enabled for the External Input chip models which are required special ordering. For normal chip model, please leave this pin NC (No connection). 6.20 VF This pin is the input of the built-in voltage regulator for generating VOUT. When external resistor network is selected (IRS pulled low) to generate the LCD driving level, VOUT, two external resistors, R1 and R2, should be connected between VSS and VF, and VF and VOUT, respectively (see application circuit diagrams). 6.21 M/ S This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected, which CL, M, MSTAT and /DOF signals will be output for slave devices. When this pin is pulled low, slave mode is selected, which CL, M, /DOF are required to be input from master device. MSTAT will still be an output signal in slave mode. 6.22 CLS This pin is the internal clock enable pin. When this pin is pulled high, internal clock is enabled. The internal clock will be disabled when it is pulled low, an external clock source must be input to CL pin for normal operation. Solomon Systech Jun 2004 P 12/52 Rev 1.1 SSD1805 Series 6.23 C68/ 80 This pin is MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is selected and when the pin is pulled low, 8080 series interface is selected. If Serial Interface is selected (P/ S pulled low), the setting of this pin is ignored, but it must be connected to a known logic (either high or low). 6.24 P/ S This pin is serial/parallel interface selection input. When this pin is pulled high, parallel interface mode is selected. When it is pulled low, serial interface will be selected. Note1: For serial mode, R/W ( WR ) must be connected to Vss. E/( RD ) must be connected to VDD. D0 to D5 and C68/80 can be connected to either VDD or VSS. Note2: Read Back operation is only available in parallel mode. 6.25 /HPM This pin is the control input of High Power Current Mode. The function of this pin is only enabled for High Power model, which required special ordering. For normal models, High Power Mode is disabled. Note: This pin must be pulled to high. Leaving this pin floating is prohibited. 6.26 IRS This is the input pin to enable the internal resistors network for the voltage regulator. When this pin is pulled high, the internal feedback resistors of the internal regulator for generating VOUT will be enabled. When it is pulled low, external resistors, R1 and R2, should be connected to VSS and VF, and VF and VOUT, respectively (see application circuit diagrams). 6.27 C1, C0 These pins are the Chip Mode Selection input. The chip mode is determined by multiplex ratio. Altogether there are four chip modes. Please see the following list for reference. C1 C0 Chip Mode 0 0 32 MUX Mode 0 1 54 MUX Mode 1 0 64 MUX Mode 1 1 68 MUX Mode Please refer to Table 3 on page 15 for detail description of common pins at different multiplex mode. 6.28 B1, B0 These pins are the Chip Mode Selection input. The chip mode is determined by default boosting level. Altogether there are four chip modes. Please see the following list for reference. B1 B0 Chip Mode 0 0 3X as POR default 0 1 4X as POR default 1 0 5X as POR default 1 1 2X as POR default 5X, 4X, 3X or 2X booster level can be selected as POR default value of the device. 6.29 ROW0 to ROW67 These pins provide the Common driving signals to the LCD panel. See Table 3 on page 15 for the COM signal mapping in different multiplex mode of SSD1805. There are ICON pins on the chip when either 64 or 54 or 32 Mux mode is selected. The ICON pins are located at the COM 0 pin and COM 67 pin. 6.30 SEG0 to SEG131 These pins provide the LCD segment driving signals. The output voltage level of these pins is VSS during sleep mode and standby mode. 6.31 TEST0 This pin is a test pin. It is recommended to connect to VSS in normal operation. SSD1805 Series Rev 1.1 P 13/52 Jun 2004 Solomon Systech 6.32 TEST1 ~ TEST22 These pins are test pins. Nothing should be connected to these pins, nor they are connected together. 6.33 NC These pins are NC/no connection pins. Nothing should be connected to these pins, nor they are connected together. Solomon Systech Jun 2004 P 14/52 Rev 1.1 SSD1805 Series Table 3 - Arrangement of common at different multiplex modes Remarks: "Non-select" means no common signal will be selected to support those output ROW pins. SSD1805 Series Rev 1.1 P 15/52 Jun 2004 Solomon Systech 7 7.1 FUNCTIONAL BLOCK DESCRIPTIONS Microprocessor Interface Logic The Microprocessor Interface unit consists of three functional blocks for driving the 6800-series parallel interface, 8080-series parallel interface and 4-wires serial peripheral interface. The selection of different interfaces is done by P/ S pin and C68/ 80 pin. Please refer to the pin descriptions on page 8. a) MPU 6800-series Parallel Interface The parallel interface consists of 8 bi-directional data pins (D7-D0), R/W ( WR ), D/ C , E( RD ), CS 1 and CS2. R/W ( WR ) input high indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/ W ( WR ) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/ C input. The E( RD ) input serves as data latch signal (clock) when high provided that CS 1 and CS2 are low and high respectively. Please refer to Figure 11 & 12 on page 40 & 41 for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of the GDDRAM with that of the MCU, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3. R/W(WR) E( RD) data bus N write column address dummy read n data read1 n+1 data read 2 n+2 data read 3 Figure 3 - Display Data Read with the insertion of dummy read b) MPU 8080-series Parallel Interface The parallel interface consists of 8 bi-directional data pins (D7-D0), E( RD ), R/W ( WR ), D/ C , CS 1 and CS2. E( RD ) input serves as data read latch signal (clock) when low provided that CS 1 and CS2 are low and high respectively. Whether reading the display data from GDDRAM or reading the status from status register is controlled by D/ C . R/W ( WR ) input serves as data write latch signal (clock) when low provided that CS 1 and CS2 are low and high respectively. Whether writing the display data to the GDDRAM or writing the command to the command register is controlled by D/ C . A dummy read is also required before the first actual display data read for 8080-series interface. Please refer to figure 13 & 14 on page 42 & 43 for Parallel Interface Timing Diagram of 8080-series microprocessors. c) MPU 4-wires Serial Interface The 4-wires serial interface consists of serial clock SCK (D6), serial data SDA (D7), D/ C , CS 1 and CS2. SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of data bit 7, data bit 6, ..., data bit 0. D/ C is sampled on every eighth clock to determine whether the data byte in the shift register is written to the Display Data RAM or command register at the same clock. Please refer to figure 15 & 16 on page 43 & 44 for serial interface timing. Remarks: For SPI mode, it is necessary to add one time of software reset command (code: E2) in the first line of the initialization code. Solomon Systech Jun 2004 P 16/52 Rev 1.1 SSD1805 Series 6800-series Parallel Interface 8080-series Parallel Interface 4-wires Serial Peripheral Interface Data Read Data Write 8-bits 8-bits 8-bits 8-bits Status only Yes No 8-bits No Yes Command Read Status only Command Write Yes Table 4 - Data Bus selection Modes 7.2 Reset Circuit This block is integrated into the Microprocessor Interface Logic that includes Power On Reset circuitry and the hardware reset pin, RES . Both of these having the same reset function. Once RES receives a negative reset pulse, all internal circuitry will start to initialize. Minimum pulse width for completing the reset sequence is 20us. Status of the chip after reset is given by: When RES input is low, the chip is initialized to the following: 1) Display ON/OFF: Display is turned OFF 2) Normal/Inverse Display: Normal Display 3) Com Scan Direction: COM0 -> COM67 4) Internal Oscillator: Enable 5) Internal DC-DC Converter: Disable 6) Bias Divider: Disable 7) Booster level: Determine by pins [B0, B1] 8) Bias ratio: 1/8 for 32 & 54 Mux mode 1/9 for 64 & 68 Mux mode 9) Multiplex ratio: Determine by pins [C0, C1] 10) Electronic volume control: 20 hex 11) Built-in resistance ratio: 24 hex o 12) Average temperature gradient: -0.05%/ C 13) Display data column address mapping: Normal 14) Display start line: GDDRAM row 0 15) Column address counter: 00 hex 16) Page address: 00 hex 17) Static indicator: Disable 18) Read-modify-write mode: Disable 19) Test mode: Disable 20) Shift register data in serial interface: Clear Note: Please find more explanation in the Applications Note attached at the back of the specification. 7.3 Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/ C pin. If D/ C pin is high, data is written to Graphic Display Data RAM (GDDRAM). If D/ C pin is low, the input at D0 - D7 is interpreted as a Command and it will be decoded. The decoded command will be written to the corresponding command register. 7.4 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 68 = 8,976bits. Table 5 on page 18 is a description of the GDDRAM address map in which the display start line register is set at 18H. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data mapped to the display. For those GDDRAM out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage. Please be noticed that the display offset cannot be greater than the default mux mode for any circumstance. SSD1805 Series Rev 1.1 P 17/52 Jun 2004 Solomon Systech Remarks: DB0 - DB7 represent the data bit of the GDDRAM. "Non-select" means no common signal will be selected to support those output ROW pins. Table 5 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 18h Solomon Systech Jun 2004 P 18/52 Rev 1.1 SSD1805 Series 7.5 LCD Driving Voltage Generator and Regulator This module generates the LCD voltage required for display driving output. It takes a single supply input and generates necessary bias voltage. It consists of: 1) 2X, 3X, 4X and 5X regulated DC-DC voltage converter The built-in DC-DC regulated voltage converter is used to generate the large positive voltage supply. SSD1805 can produce 2X, 3X, 4X or 5X boosting from the potential different between VSS1 - VCI. No external boosting capacitors are required for configuration. Please refer to the command table for detail description. The feedback gain control for LCD driving contrast curves can be selected by IRS pin to either internal (IRS pin = H) or external (IRS pin = L). If internal resistor network is enabled, eight settings can be selected through software command. If external control is selected, external resistors are required to connect between Vss and VF (R1), and between VF and VOUT (R2). See application circuit diagrams for detail connections. VOUT + C2 + C1 VHREF VDD VCI SSD1805 VLREF VSS Normal Power Mode Recommended capacitance value: C1: 1uF ~ 2.2uF C2: 2.2uF ~ 4.7uF VOUT + C2 + C1 VHREF VDD VCI SSD1805 Low Power Mode In Low Power Mode, TEST4 must > 4V Recommended capacitance value: C1: 1uF ~ 2.2uF C2: 2.2uF ~ 4.7uF VLREF VSS Figure 4 - SSD1805 Hardware configuration 2) Bias Divider If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VOUT) to give the LCD driving levels. The divider does not require external capacitors to reduce the external hardware and pin counts. 3) Bias Ratio Selection circuitry The software control circuit of 1/4 to 1/9 bias ratio in order to match the characteristic of LCD panel. SSD1805 Series Rev 1.1 P 19/52 Jun 2004 Solomon Systech 4) Contrast Control (Voltages referenced to VSS) Software control of the 64 contrast voltage levels at each voltage regulator feedback gain. The equation of calculating the LCD driving voltage is given as: Command Set Gain = 1+R2/R1 000 4.96 001 5.70 010 6.54 011 7.41 100 8.33 101 8.95 110 10.05 111 11.01 Table 6 - Gain Setting R Vout = 1 + 2 *Vcon R 1 121 - Vcon = 1 - * Vref 210 where Vref = 1.6 and = contrast setting Please refer to figure 5 on page 21 for the contrast curve with 8 sets of internal resistor network gain. 5) Self adjust temperature compensation circuitry Provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (TC) value is -0.05%/C. TC Settings TC0 TC2 TC4 TC7 Temperature compensation coefficient [%/ C] -0.05 -0.15 -0.20 -0.25 o Vref typical value [V] 1.60 1.70 1.75 1.85 Table 7 - Temperature compensation coefficient Solomon Systech Jun 2004 P 20/52 Rev 1.1 SSD1805 Series Figure 5 - Contrast curve SSD1805 Series Rev 1.1 P 21/52 Jun 2004 Solomon Systech 7.6 Oscillator Circuit This module is an On-Chip low power temperature compensation oscillator circuitry. The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator. Please refer to the figure 6 for the typical frame frequency at different temperature. Figure 6 - Oscillator typical frame frequency with variation in temperature 7.7 Display Data Latch This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level. The numbers of latches of different members are given by: 32 Mux mode: 132 + 33 = 165 54 Mux mode: 132 + 55 = 187 64 Mux mode: 132 + 65 = 197 68 Mux mode: 132 + 68 = 200 7.8 HV Buffer Cell (Level Shifter) This block is embedded in the Segment/Common Driver Circuits. HV Buffer Cell works as a level shifter, which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock, which comes from the Display Timing Generator. The voltage levels are given by the level selector that is synchronized with the internal M signal. 7.9 Level Selector This block is embedded in the Segment/Common Driver Circuits. Level Selector is a control of the display synchronization. Display voltage levels can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. Solomon Systech Jun 2004 P 22/52 Rev 1.1 SSD1805 Series 7.10 LCD Panel Driving Waveform Figure 7 is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms provided illustrate the desired multiplex scheme. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 TI ME SLOT . .. * N123456789 .. . * N1 2 3 4 5 6 7 8 9 .. . * N 123456789 .. . * N1 2 3 4 5 6 7 8 9 V o ut V L5 COM0 V L4 V L3 V L2 VS S V o ut V L5 COM1 V L4 V L3 V L2 VS S V o ut V L5 SEG0 V L4 V L3 V L2 VS S V o ut V L5 SEG1 V L4 V L3 V L2 VS S M *Note: N is the number of multiplex ratio including Icon line if it is enabled; N is equal to 68 on POR. * Note : N is the number of multiplex ratio including Icon line if it is enabled, N is equal to 64 on POR . Figure 7 - LCD Driving Waveform SSD1805 Series Rev 1.1 P 23/52 Jun 2004 Solomon Systech 8 COMMAND TABLE Table 8 - Command Table (D/ C = 0, R/ W ( WR ) = 0, E=1( RD = 1) unless specific setting is stated) D/C Hex 0 00 - 0F D7 D6 D5 D4 0 0 0 0 D3 X3 D2 X2 D1 X1 D0 X0 Command Set Lower Column Address Description Set the lower nibble of the column address register using X3X2X1X0 as data bits. The lower nibble of column address is reset to 0000b after POR. Set the higher nibble of the column address register using X3X2X1X0 as data bits. The higher nibble of column address is reset to 0000b after POR. 0 10 - 1F 0 0 0 1 X3 X2 X1 X0 Set Higher Column Address 0 20 - 27 0 0 1 0 0 X2 X1 X0 0 28 - 2F 0 0 1 0 1 X2 1 X0 0 0 40 - 7F 0 * 1 Y6 X5 Y5 X4 Y4 X3 Y3 X2 Y2 X1 Y1 X0 Y0 0 84 - 87 1 0 0 0 0 1 X1 X0 0 0 81 1 0 0 0 0 X5 0 X4 0 X3 0 X2 0 X1 1 X0 0 A0 - A1 1 0 1 0 0 0 0 X0 0 A2 - A3 1 0 1 0 0 0 1 X0 0 0 A4 - A5 A6 - A7 1 1 0 0 1 1 0 0 0 0 1 1 0 1 X0 X0 Feedback gain of the internal regulated DC-DC converter for generating VOUT increases as X2X1X0 increased from 000b to 111b. After POR, X2X1X0 = 100b. Set Power X0=0: turns off the output op-amp buffer (POR) Control Register X0=1: turns on the output op-amp buffer X2=0: turns off the internal voltage booster (POR) X2=1: turns on the internal voltage booster Set Display Start For 68 MUX mode, set X5X4X3X2X1X0 = 111111 and set Line the GDDRAM display start line register from 0-67 using Y6Y5Y4Y3Y2Y1Y0 For 64/54/32 MUX modes, set GDDRAM display start line register from 0-63 using X5X4X3X2X1X0. There is no need to send the Y6Y5Y4Y3Y2Y1Y0 parameters. Display start line register is reset to 000000 after POR for all MUX modes. Set Boost Level Set the DC-DC multiplying factor from 2X to 5X. X1X0: 00: 3X 01: 4X 10: 5X 11: 2X Remarks: The POR default boosting level is determined by hardware selection pin, B0 & B1. Set Contrast Select contrast level from 64 contrast steps. Contrast Control Register increases (VOUT decreases) as X5X4X3X2X1X0 is increased from 000000b to 111111b. X5X4X3X2X1X0 = 100000b after POR X0=0: column address 00h is mapped to SEG0 (POR) Set Segment ReX0=1: column address 83h is mapped to SEG0 map Refer to Table 5 on page 16 for example. Set LCD Bias X0=0: POR default bias: 32 MUX mode = 1/8 54 MUX mode = 1/8 64 MUX mode = 1/9 68 MUX mode = 1/9 X0=1: alternate bias: 32 MUX mode = 1/6 54 MUX mode = 1/6 64 MUX mode = 1/7 68 MUX mode = 1/7 For other bias ratio settings, see "Set 1/4 Bias Ratio" and "Set Bias Ratio" in Extended Command Set. Set Entire X0=0: normal display (POR) Display On/Off X0=1: entire display on Set X0=0: normal display (POR) Normal/Reverse X0=1: reverse display Display Set Internal Gain Resistor Ratio Solomon Systech Jun 2004 P 24/52 Rev 1.1 SSD1805 Series D/C Hex D7 D6 D5 D4 0 AE - AF 1 0 1 0 0 0 B0 - B8 C0 - C8 1 1 0 1 1 0 1 0 D3 1 X3 X3 D2 1 X2 * D1 1 X1 * D0 X0 X0 * 0 E0 1 1 1 0 0 0 0 0 0 0 E2 EE 1 1 1 1 1 1 0 0 0 1 0 1 1 1 0 0 0 0 AC - AD 1 * 0 * 1 * 0 * 1 * 1 * 0 Y1 X0 Y0 Description X0=0: turns off LCD panel (POR) X0=1: turns on LCD panel Set GDDRAM Page Address (0-8) for read/write using X3X2X1X0 X3=0: normal mode (POR) X3=1: remapped mode, COM0 to COM [N-1] becomes COM [N-1] to COM0 when Multiplex ratio is equal to N. See Table 5 on page 16 for detail mapping. Set Read-Modify- Read-Modify-Write mode will be entered in which the Write Mode column address will not be increased during display data read. After POR, Read-modify-write mode is turned OFF. Software Reset Initialize internal status registers. Set End of Read- Exit Read-Modify-Write mode. RAM Column address Modify-Write before entering the mode will be restored. After POR, Mode Read-modify-write mode is OFF. Indicator Display X0 = 0: indicator off (POR, second command byte is not required) Mode X0 = 1: indicator on (second command byte required) Y1Y0 = 00: indicator off Y1Y0 = 01: indicator on and blinking at ~1 second interval Y1Y0 = 10: indicator on and blinking at ~1/2 second interval Y1Y0 = 11: indicator on constantly This second byte command is required ONLY when "Set Indicator On" command is sent. NOP Command result in No Operation. Set Test Mode Reserved for IC testing. Do NOT use. Set Power Save Either standby or sleep mode will be entered using Mode compound commands. Issue compound commands "Set Display Off" followed by "Set Entire Display On". Standby mode will be entered when the static indicator is on constantly. Sleep mode will be entered when static indicator is off. Command Set Display On/Off Set Page Address Set COM Output Scan Direction 0 0 0 0 0 0 E3 F0 - FF AE A5 1 1 1 1 1 * 1 1 0 0 0 * 1 1 1 1 1 * 0 1 0 0 0 * 0 * 1 0 1 * 0 * 1 1 1 * 1 * 1 0 0 X1 1 * 0 1 X0 X0 SSD1805 Series Rev 1.1 P 25/52 Jun 2004 Solomon Systech EXTENDED COMMAND TABLE Table 9 - Extended Command Table(D/ C = 0,R/W ( WR ) = 0,E=1( RD = 1) unless specific setting is stated) D/C 0 0 Hex 82 D7 D6 D5 D4 1 0 0 0 * 0 0 0 D3 0 X3 D2 0 X2 D1 1 X1 D0 0 X0 Command OTP Setting Description X3X2X1X0: OTP fuse value 0000 : original contrast 0001 : original contrast + 1 steps 0010 : original contrast + 2 steps 0011 : original contrast + 3 steps 0100 : original contrast + 4 steps 0101 : original contrast + 5 steps 0110 : original contrast + 6 steps 0111 : original contrast + 7 steps 1000 : original contrast - 8 steps 1001 : original contrast - 7 steps 1010 : original contrast - 6 steps 1011 : original contrast - 5 steps 1100 : original contrast - 4 steps 1101 : original contrast - 3 steps 1110 : original contrast - 2 steps 1111 : original contrast - 1 steps This command starts to program LCD driver with OTP offset value. Each bit can be programmed to 1 once. Detail of OTP programming procedure on page 31 To select multiplex ratio N from 2 to the maximum multiplex ratio (POR value) for each member (including icon line for 65 MUX mode). Max. MUX ratio: 68 MUX: 68 N = X6X5X4X3X2X1X0 + 1 + ICON*, (*ICON exist for 64/54/32 MUX mode) e.g. N = 001111b + 2 = 17 01 10 11 MUX X1X0 = 00 32 : 1/8 or 1/6(POR) 1/6 or 1/5 1/9 or 1/7 P 54 : 1/8 or 1/6(POR) 1/6 or 1/5 1/9 or 1/7 P 64 : 1/8 or 1/6 1/6 or 1/5 1/9 or 1/7(POR) P 68 : 1/8 or 1/6 1/6 or 1/5 1/9 or 1/7(POR) P P stands for prohibited settings X4X3X2 = 000: (TC0) Typ. -0.05 (POR) X4X3X2 = 010: (TC2) Typ. -0.15 X4X3X2 = 100: (TC4) Typ. -0.20 X4X3X2 = 111: (TC7) Typ. -0.25 Increase the value of X7X6X5 will increase the oscillator frequency and vice versa. Default Mode: Osc Frequency (Hz) X7X6X5 000 61 001 64 010 68 011 72 (POR) 100 75 101 80 110 90 111 98 Remarks: By software program the multiplex ratio, the typical oscillator frequency is listed above. X0 = 0: use normal setting (POR) X0 = 1: fixed at 1/4 bias regardless of other bias setting commands 0 83 1 0 0 0 0 0 1 1 OTP Programming Set Multiplex Ratio 0 0 A8 1 0 0 X6 1 X5 0 X4 1 X3 0 X2 0 X1 0 X0 0 0 A9 1 X7 0 X6 1 X5 0 X4 1 X3 0 X2 0 X1 1 X0 Set Bias Ratio Set TC Value Modify Osc. Freq. 0 AA - AB 1 0 1 0 1 0 1 X0 Set 1/4 Bias Ratio Solomon Systech Jun 2004 P 26/52 Rev 1.1 SSD1805 Series D/C Hex D7 D6 D5 D4 0 D0 - D1 1 1 0 1 0 0 D3 1 0 1 X6 0 X5 1 X4 D3 0 0 X3 D2 0 0 X2 D1 0 1 X1 D0 X0 1 X0 Command Set icon enabled Set Display Offset Set Total Frame Phases 0 0 D4 1 0 1 0 0 X5 1 X4 0 0 1 0 0 0 0 0 Set Display Offset Description X0 = 0: icon is off. X0 = 1: icon is on. (POR) After POR, X6X5X4X3X2X1X0 = 0 After setting MUX ratio less than default value, data will be displayed at the beginning/towards the end of display matrix. To move display towards Row 0 by L, X6X5X4X3X2X1X0 =L To move display away from Row 0 by L, X6X5X4X3X2X1X0 = Y-L Note: max. value of L = POR default MUX ratio - display MUX Note: Y represents POR default MUX ratio The On/Off of the Static Icon is given by 3 phases / 1 phase overlapping of the M and MSTAT signals. This command set total phases of the M/MSTAT signals for each frame. The more the total phases, the less the overlapping time and thus the lower the effective driving voltage. X5X4 = 00: 5 phases X5X4 = 01: 7 phases X5X4 = 10: 9 phases (POR) X5X4 = 11: 16 phases After POR, X6X5X4X3X2X1X0 = 0 After setting MUX ratio less than default value, data will be displayed at the beginning/towards the end of display matrix. To move display towards Row 0 by L, X6X5X4X3X2X1X0 =L To move display away from Row 0 by L, X6X5X4X3X2X1X0 = Y-L Note: max. value of L = POR default MUX ratio - display MUX Note: Y represents POR default MUX ratio READ COMMAND TABLE Table 10 - Read Command Table (D/ C = 1, R/W ( WR ) = 1, E=1( RD = 0) unless specific setting is stated) D/C 1 Hex 00 - FF D7 D6 D5 D4 X7 X6 X5 0 D3 X3 D2 X2 D1 X1 D0 X0 Command Status Register Read Description X7=0: indicates the driver is ready for command. X7=1: indicates the driver is Busy. X6=0: indicates normal segment mapping with column address. X6=1: indicates reverse segment mapping with column address. X5=0: indicates the display is ON. X5=1: indicates the display is OFF. X3X2X1X0 = 0010, the 4-bit is fixed to 0010 which could be used to identify as Solomon Systech Device. Note: Command patterns other than that given in Command Table and Extended Command Table are prohibited. Otherwise, unexpected result will occur. SSD1805 Series Rev 1.1 P 27/52 Jun 2004 Solomon Systech 9 9.1 COMMAND DESCRIPTIONS Data Read / Write To read data from the GDDRAM, input High to R/W ( WR ) pin and D/ C pin for 6800-series parallel mode, input Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided in serial interface mode. In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read. However, no automatic increase will be performed in read-modify-write mode. Also, a dummy read is required before first valid data is read. See Figure 3 on page 15 in Functional Block Descriptions section for detail waveform diagram. To write data to the GDDRAM, input Low to R/W ( WR ) pin and High to D/ C pin for both 6800-series and 8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. It should be noted that, after the automatic column address increment, the pointer will NOT wrap round to 0. The pointer will exit the memory address space after accessing the last column. Therefore, the pointer should be re-initialized when progress to another page address. D/ C 0 0 1 1 R/W ( WR ) 0 1 0 1 Action Write Command Read Status Write Data Read Data Auto Address Increment No No Yes Yes Table 11 - Automatic Address Increment 9.2 Set Lower Column Address This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU. 9.3 Set Higher Column Address This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU. 9.4 Set Internal Gain Resistors Ratio This command is to enable any one of the eight internal resistor sets for different gains when using internal resistor network (IRS pin pulled high). In other words, this command is used to select which contrast curve from the eight possible selections. Please refer to Functional Block Descriptions section for detail calculation of the LCD driving voltage. 9.5 Set Power Control Register This command turns on/off the various power circuits associated with the chip. There are two related power sub-circuits could be turned on/off by this command. Internal voltage booster is used to generate the positive voltage supply (VOUT) from the voltage input (VCI - VSS1). An external positive power supply is required if this option is turned off. Output op-amp buffer is the internal divider for dividing the different voltage levels from the internal voltage booster, VOUT. External voltage sources should be fed into this driver if this circuit is turned off. 9.6 Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 67. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0 and so on. Display start line values of 0 to 67 are assigned to Page 0 to 8. Please refer to Table 5 on Page 17 as an example for display start line set to 24 (18h). Solomon Systech Jun 2004 P 28/52 Rev 1.1 SSD1805 Series 9.7 Set Boost level The internal DC-DC converter factor is set by this command. For SSD1805, 2X to 5X multiplying factors could be selected. The default POR internal DC-DC converter setting can be selected by hardware pin, B0 & B1. 9.8 Set Contrast Control Register This command adjusts the contrast of the LCD panel by changing the LCD driving voltage, VOUT, provided by the On-Chip power circuits. VOUT is set with 64 steps (6-bit) in the contrast control register by a set of compound commands. See Figure 8 for the contrast control flow. Set Contrast Control Register No Contrast Level Data Changes Complete? Yes Figure 8 - Contrast Control Flow 9.9 Set Segment Re-map This command changes the mapping between the display data column addresses and segment drivers. It allows flexibility in mechanical layout of LCD glass design. Please refer to Table 5 on Page 15 for example. 9.10 Set LCD Bias This command is used to select a suitable bias ratio required for driving the particular LCD panel in use. The selectable values of this command for 68/64 MUX are 1/9 or 1/7, 54/32 MUX are 1/8 or 1/6. For other bias ratio settings, extended commands should be used. 9.11 Set Entire Display On/Off This command forces the entire display, including the icon row, to be illuminated regardless of the contents of the GDDRAM. In addition, this command has higher priority than the normal/reverse display. This command is used together with "Set Display ON/OFF" command to form a compound command for entering power save mode. See "Set Power Save Mode" later in this section. 9.12 Set Normal/Reverse Display This command turns the display to be either normal or reverse. In normal display, a RAM data of 1 indicates an illumination on the corresponding pixel. While in reverse display, a RAM data of 0 will turn on the pixel. It should be noted that the icon line will not affect, that is not reverse by this command. 9.13 Set Display On/Off This command is used to turn the display on or off. When display off is issued with entire display is on, power save mode will be entered. See "Set Power Save Mode" later in this section for details. 9.14 Set Page Address This command enters the page address from 0 to 8 to the RAM page register for read/write operations. Please refer to Table 5 on Page 17 for detail mapping. 9.15 Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. See Table 5 on Page 17 for the relationship between turning on or off of this feature. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will have vertical flipping effect. SSD1805 Series Rev 1.1 P 29/52 Jun 2004 Solomon Systech 9.16 Set Read-Modify-Write Mode This command puts the chip in read-modify-write mode in which: 1. Column address is saved before entering the mode 2. Column address is increased only after display data write but not after display data read. This Read-Modify-Write mode is used to save the MCU's loading when a very portion of display area is being updated frequently. As reading the data will not change the column address, it could be get back from the chip and do some operation in the MCU. Then the updated data could be written back to the GDDRAM with automatic address increment. After updating the area, "Set End of Read-Modify-Write Mode" is sent to restore the column address and ready for next update sequence. 9.17 Software Reset Issuing this command causes some of the chip's internal status registers to be initialized: Read-Modify-Write mode is off Static indicator is turned OFF Display start line register is cleared to 0 Column address counter is cleared to 0 Page address is cleared to 0 Normal scan direction of the COM outputs Internal gain resistors Ratio is set to 4 Contrast control register is set to 20h 9.18 Set End of Read-Modify-Write Mode This command relieves the chip from read-modify-write mode. The column address before entering readmodify-write mode will be restored no matter how much modification during the read-modify-write mode. 9.19 Set Indicator On/Off This command turns on or off the static indicator driven by the M and MSTAT pins. When the "Set Indicator On" command is sent, the second command byte "Indicator Display Mode" must be followed. However, the "Set Indicator Off" command is a single byte command and no second byte command is required. The status of static indicator also controls whether standby mode or sleep mode will be entered, after issuing the power save compound command. See "Set Power Save Mode" later in this section. 9.20 NOP A command causing the chip takes No Operation. 9.21 Set Test Mode This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, users should NOT use this command. 9.22 Set Power Save Mode Entering Standby or Sleep Mode should be done by using a compound command composed of "Set Display ON/OFF" and "Set Entire Display ON/OFF" commands. When "Set Entire Display ON" is issued when display is OFF, either Standby Mode or Sleep Mode will be entered. The status of the Static Indicator will determine which power save mode is entered. If static indicator is off, the Sleep Mode will be entered: Internal oscillator and LCD power supply circuits are stopped Segment and Common drivers output VSS level The display data and operation mode before sleep are held Internal display RAM can still be accessed If the static indicator is on, the chip enters Standby Mode that is similar to sleep mode except addition with: Internal oscillator is on Static drive system is on Please also be noted that during Standby Mode, if the software reset command is issued, Sleep Mode will be entered. Both power save modes can be exited by the issue of a new software command or by pulling Low at hardware pin RES . Solomon Systech Jun 2004 P 30/52 Rev 1.1 SSD1805 Series EXTENDED COMMANDS These commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip. 9.23 OTP setting and programming OTP (One Time Programming) is a method to adjust VOUT. In order to eliminate the variations of LCD module in term of contrast level, OTP can be used to achieve the best contrast of every LCD modules. OTP setting and programming should include two major steps. Find the OTP offset and OTP programming as following, Step 1. Find OTP offset Hardware Reset (sending an active low reset pulse to RES pin) Send original initialization routines Set and display any test patterns Adjust the contrast value 0x81, 0x00~0x3Funtil there is the best visual contrast OTP setting steps = Contrast value of the best visual contrast - Contrast value of original initialization Example 1 Contrast value of original initialization = 0x20 Contrast value of the best original initialization = 0x24 OTP offset value = 0x24 - 0x20 = +4 OTP setting command should be (0x82, 0x04) Example 2: Contrast value of original initialization = 0x20 Contrast value of the best original initialization = 0x1B OTP setting = 0x1B - 0x20 = -6 OTP setting command should be (0x82, 0x0A) Step 2. OTP programming Hardware Reset (sending an active low reset pulse to RES pin) Connect an external VOUT (see diagram below) Send OTP setting commands that we find in step 1 (0x82, 0x00~0X0F) Send OTP programming command (0x83) Wait at least 2 seconds Hardware Reset Verify the result by repeating step 1. (2) - (3) SSD1805 (8) R +C GND VOUT 14.5-15.5V (1) & (6) & GND RES Note: R = 1K ~ 10k ohm C = 1u ~ 4.7u F Figure 9 - OTP programming circuitry SSD1805 Series Rev 1.1 P 31/52 Jun 2004 Solomon Systech Start Step 2 Step 1 i) Hardware reset ii) Send original initialization routines iii) Set and display any test patterns i) Hardware reset ii) Enable oscillator Adjust the contrast level to the best visual level Connect an external voltage (14.5~15.5V) on VOUT pins Accept the contrast level on panel? No i) Send OTP setting commands ii) Send OTP programming command iii) Wait > 2 sec iv) Hardware reset Yes OTP setting steps = Adjusted contrast value - Original contrast value i) Send original initialization routines ii) Set and display any test patterns iii) Inspect the contrast END Figure 10 - Flow chart of OTP programming Procedure Solomon Systech Jun 2004 P 32/52 Rev 1.1 SSD1805 Series OTP Example program Find the OTP offset: Hardware reset by sending an active low reset pulse to RES pin 0X2F \\ turn on the internal voltage booster & output op-amp buffer. 0XA2 \\ Set Biasing ratio 0XA9 \\ 1/9 for 68/64 MUX mode 0X62 0X81 \\Set target gain and contrast. 0X20 \\ contrast = 20 Hex. 0X24 \\ IR4 => \\ Set target display contents 0x00 \\ set start column address at 0000 binary for lower nibble 0X10 \\ set start column address at 0000 binary for upper nibble 0XB0 \\ set page address at page 0 0xAF \\ display on OTP offset calculation... target OTP offset value is +6 OTP programming: Hardware reset by sending an active low reset pulse to RES pin Connect a external VOUT (14.5V~15.5V) 0X82 \\ Set OTP offset value to +6 (0110) 0X06 \\ 0000 X3X2X1X0 , where X3X2X1X0 is the OTP offset value 0X83 \\ Send the OTP programming command. Wait at least 2 seconds for programming wait time. Verify the result: After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel. 9.24 Set Multiplex Ratio This command switches default multiplex ratio to any multiplex mode from 2 to the maximum multiplex ratio (POR value), including the icon line. Max. MUX ratio: 68 for 68 MUX mode 65 for 64 MUX mode including icon line 55 for 54 MUX mode including icon line 33 for 32 MUX mode including icon line The chip pins ROW0 - ROW67 will be switched to corresponding COM signal output, see Table 12 on Page 35 for examples with and without 8 lines display offset for different MUX. It should be noted that after changing the display multiplex ratio, the bias ratio need to be adjusted to make display contrast consistent. 9.25 Set Bias Ratio Except the 1/4 bias, all other available bias ratios could be selected using this command plus the "Set LCD Bias" command. For detail setting values and POR default, please refer to the extended command table, Table 9 on Page 26. 9.26 Set Temperature Coefficient (TC) Value One out of 4 different temperature coefficient settings is selected by this command in order to match various liquid crystal temperature grades. Please refer to the extended command table, Table 9 on Page 26, for detailed TC values. 9.27 Modify Oscillator Frequency The oscillator frequency can be fine tuned by applying this command. Since the oscillator frequency will be affected by some other factors, this command is not recommended for general usage. Please contact Solomon Systech application engineers for more detail explanation on this command. SSD1805 Series Rev 1.1 P 33/52 Jun 2004 Solomon Systech 9.28 Set 1/4 Bias Ratio This command sets the bias ratio directly to 1/4. This bias ratio is especially designed for use in under 12 MUX display. In order to restore to other bias ratio, this command must be executed, with LSB=0, before the "Set Multiplex ratio" or "Set LCD Bias" command is sent. 9.29 Set Icon Enabled This command enables or disables the icon. It should be noticed that the default setting (POR) will enable the icon. 9.30 Set Display Offset This command should be sent ONLY when the multiplex ratio is set less than the default value. When a lesser multiplex ratio is set, the display will be mapped in the top (y-direction) of the LCD, see the no offset columns on Table 3 on Page 15. Use this command could move the display vertically within the 67 commons. To make the Reduced-MUX Com 0 (Com 0 after reducing the multiplex ratio) towards the Row 0 direction for L lines, the 7-bit data in second command should be given by L. An example for 8 line moving towards to Com 0 direction is given on Table 12 on Page 35. To move in the other direction by L lines, the 8bit data should be given by 67-L. Please note that the display is confined within the default multiplex value. 9.31 Set Total Frame Phases The total number of phases for one display frame is set by this command. The Static Icon is generated by the overlapping of M and MSTAT signals. These two pins output either VSS or VDD at same frequency but with phase different. To turn on the Static Icon, 3 phases overlapping is applied to these signals, while 1 phase overlapping is given to the off status. The more the total number of phases in one frame, the less the overlapping time. Thus the lower the effective driving voltage at the Static Icon on the LCD panel. 9.32 Status register Read This command is issued by pulling D/ C Low during a data read (refer to Figure 11 on Page 40 and Figure 13 on Page 42 for parallel interface waveforms). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode. Solomon Systech Jun 2004 P 34/52 Rev 1.1 SSD1805 Series Table 12 - ROW pin assignment for COM signals for SSD1805 in a 68 MUX display (including icon line without/with 8 lines display offset towards ROW0) Remarks: "Non-select" means no common signal will be selected to support those output ROW pins. SSD1805 Series Rev 1.1 P 35/52 Jun 2004 Solomon Systech 10 MAXIMUM RATINGS Table 13 - Maximum Ratings (Voltage Referenced to VSS) Symbol VDD VDDIO VOUT VCI I TA Tstg Ron Parameter Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Input Resistance Value -0.3 to +4.0 -0.3 to + 4.0 0 to +15.0 VSS-0.3 to 4.0 25 -30 to +85 -65 to +150 1000 Unit V V V V mA C C ohm o o Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VCI and VOUT be constrained to the range VSS < or = (VCI or VOUT) < or = VDD. Reliability of operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. Solomon Systech Jun 2004 P 36/52 Rev 1.1 SSD1805 Series 11 DC CHARACTERISTICS Table 14 - DC Characteristics Symbol VDD VDDIO VCI Parameter System power supply pins of the logic block Range System power supply pins of the logic block Range Booster Reference Supply Voltage Range Access Mode Supply Current Drain (VDD Pins) Test Condition Recommend Operating Voltage Possible Operating Voltage Recommend Operating Voltage Possible Operating Voltage Recommend Operating Voltage Possible Operating Voltage VDD = 2.7V, Voltage Generator On, 4X DC-DC Converter Enabled, Write accessing, Tcyc =3.3MHz, Typ. Osc. Freq., Display On, no panel attached. VDD = 2.7V, VOUT = 9V, regulated DC-DC Converter Disabled, R/W ( WR ) Halt, Typ. Osc. Freq., Display On, no panel attached. VDD = 2.7V, VOUT = 9V, Voltage Generator On, 4X DC-DC Min 1.8 1.2 VDD Typ 2.7 Max 3.6 VDD 3.6 Unit V V V IAC - 450 750 A IDP1 Display Mode Supply Current Drain (VDD Pins) - 70 150 A IDP2 ISB ISLEEP VOUT VLCD VOH1 VOL1 VIH1 VIL1 IOH IOL IOZ IIL/IIH CIN VOUT Converter Enabled, R/W ( WR ) Halt, Typ. Osc. Freq., Display On, no panel attached. VDD = 2.7V, LCD Driving Waveform Standby Mode Supply Current Off, Typ. Osc. Freq., R/W ( WR ) Drain (VDD Pins) halt. VDD = 2.7V, LCD Driving Waveform Sleep Mode Supply Current Drain (VDD Pins) Off, Oscillator Off, R/W ( WR ) halt. Display On, Voltage Generator LCD Driving Voltage Generator 1.8 Enabled, DC-DC Converter Output (VOUT Pin) Enabled, Typ. Osc. Freq., Regulator Enabled, Divider Enabled. 93 VOUT Converter Efficiency 5X boosting, no panel loading LCD Driving Voltage Input Voltage Generator Disabled. 1.8 (VOUT Pin) Logic High Output Voltage IVOUT = -100uA 0.9* VDDIO Logic Low Output Voltage IVOUT = 100uA 0 Logic High Input voltage 0.8* VDDIO Logic Low Input voltage 0 Logic High Output Current VOUT = VDD-0.4V 50 Source VOUT = 0.4V Logic Low Output Current Drain Logic Output Tri-state Current -1 Drain Source Logic Input Current -1 Logic Pins Input Capacitance Regulated DC-DC Converter Variation of VOUT Output (VDD is Enabled, Internal Contrast Control -2 fixed) Enabled, Set Contrast Control Register = 0 Display Mode Supply Current Drain (VDD Pins) 400 700 A 45 5 - 70 10 12.5 A A V 99 5 0 12.0 VDDIO 0.1* VDDIO VDDIO 0.2* VDDIO -50 1 1 7.5 2 % V V V V V A A A A pF % SSD1805 Series Rev 1.1 P 37/52 Jun 2004 Solomon Systech Symbol TC0 TC2 TC4 TC7 Parameter Temperature Coefficient Compensation Flat Temperature Coefficient (POR) Temperature Coefficient 2* Temperature Coefficient 4* Temperature Coefficient 7* Test Condition Min 0 Typ Max Unit %/ C %/ C o %/ C o %/ C o o -0.05 -0.10 -0.15 -0.17 -0.20 -0.22 -0.25 -0.27 Regulated DC-DC Converter Enabled -0.11 -0.18 -0.23 The formula for the temperature coefficient is: TC(%) = Vref at 50 o C - Vref at0 o C 1 x x100% o o 50 C - 0 C Vref at 25 o C Solomon Systech Jun 2004 P 38/52 Rev 1.1 SSD1805 Series 12 AC CHARACTERISTICS Table 15 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD =2.7V, TA = -30 to 85C) Symbol Fosc Parameter Oscillation Frequency of Display Timing Generator Test Condition Min Internal Oscillator Enabled (default), VDD = 2.7V Remark: 4.4 Oscillation Frequency vs. Temperature change (-20C to 70C): -0.05%/C * 132 x 68 Graphic Display Mode, Display ON, Internal Oscillator Enabled 132 x 68 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. Typ Max Unit 4.9 5.4 kHz FFRM Frame Frequency 72 Hz 653k Hz Remarks: Fext stands for the frequency value of external clock feeding to the CL pin. Fosc stands for the frequency value of internal oscillator. Frequency limits are based on the software command set: set multiplex ratio to 68 MUX SSD1805 Series Rev 1.1 P 39/52 Jun 2004 Solomon Systech Table 16 - Parallel 6800-series Interface Timing Characteristics (TA = -35 to 85C, VDD = VCI = 1.8V to 3.6V, VDDIO = 1.2V to VDD) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 200 0 0 40 10 10 15 15 500 500 100 200 100 Typ 1000 Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D/C tAS R/W tAH CS tF tcycle PW CSH tR E tDSW D0~D7(Write) tACC D0~D7(Read) Valid Data Valid Data tDHR PW CSL tDHW The PW CSH timing reference is 50% of the rising / falling edge of E or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of E or CS pin. tOH Figure 11 - Parallel 6800-series Interface Timing Characteristics (P/S = H, C68/80 = H) Solomon Systech Jun 2004 P 40/52 Rev 1.1 SSD1805 Series Table 17 - Parallel 6800-series Interface Timing Characteristics (TA = -35 to 85C, VDD = VCI = VDDIO = 1.8V to 3.6V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 30 5 10 15 15 250 250 50 100 50 Typ 500 Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D/C tAS R/W tAH CS tF tcycle PW CSH tR E tDSW D0~D7(Write) tACC D0~D7(Read) Valid Data Valid Data tDHR PW CSL tDHW The PW CSH timing reference is 50% of the rising / falling edge of E or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of E or CS pin. tOH Figure 12 - Parallel 6800-series Interface Timing Characteristics (P/S = H, C68/80 = H) SSD1805 Series Rev 1.1 P 41/52 Jun 2004 Solomon Systech Table 18 - Parallel 8080-series Interface Timing Characteristics (TA = -35 to 85C, VDD = VCI = 1.8V to 3.6V, VDDIO = 1.2V to VDD) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 200 0 0 40 10 10 15 15 500 500 100 200 100 Typ 1000 Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle D/C tAS tAH tR tcycle PW CSL PW CSH CS tF WR RD tDSW tDHW D0-D7(WRITE) Valid Data The PW CSL timing reference is 50% of the rising / falling edge of WR or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of WR or CS pin. Read Cycle D/C tAS tAH tR CS tF WR PW CSL tcycle PW CSH RD tACC tDHR Valid Data tOH D0-D7(READ) The PW CSL timing reference is 50% of the rising / falling edge of RD or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of RD or CS pin. Figure 13 - Parallel 8080-series Interface Timing Characteristics (P/S = H, C68/80 = L) Solomon Systech Jun 2004 P 42/52 Rev 1.1 SSD1805 Series Table 19 - Parallel 8080-series Interface Timing Characteristics (TA = -35 to 85C, VDD = VCI = VDDIO = 1.8V to 3.6V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (Command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 30 5 10 15 15 250 250 50 100 50 Typ 500 Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle D/C tAS tAH tR tcycle PW CSL PW CSH CS tF WR RD tDSW tDHW D0-D7(WRITE) Valid Data The PW CSL timing reference is 50% of the rising / falling edge of WR or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of WR or CS pin. Read Cycle D/C tAS tAH tR CS tF WR PW CSL tcycle PW CSH RD tACC tDHR Valid Data tOH D0-D7(READ) The PW CSL timing reference is 50% of the rising / falling edge of RD or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of RD or CS pin. Figure 14 - Parallel 8080-series Interface Timing Characteristics (P/S = H, C68/80 = L) SSD1805 Series Rev 1.1 P 43/52 Jun 2004 Solomon Systech Table 20 - 4-wires Serial Interface Timing Characteristics (TA = -35 to 85C, VDD = VCI = 1.8V to 3.6V, VDDIO = 1.2V to VDD) Symbol tcycle tAS tAH tDSW tDHW TCLKL TCLKH tCSS tCSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Chip Select Setup Time (for D7 input) Chip Select Hold Time (for D0 input) Rise Time Fall Time Min 111 15 10 60 60 55.5 55.5 60 55.5 Typ Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns D/C tAS tAH tCSH tcycle CS tCSS tCLKL tCLKH SCK(D6) tF tDSW tR tDHW SDA(D7) Valid Data CS SCK(D6) SDA(D7) D7 D6 D5 D4 D3 D2 D1 D0 Figure 15 - 4-wires Serial Interface Timing Characteristics (P/S = L, C68/80 = L) Solomon Systech Jun 2004 P 44/52 Rev 1.1 SSD1805 Series Table 21 - 4-wires Serial Interface Timing Characteristics (TA = -35 to 85C, VDD = VCI = VDDIO = 1.8V to 3.6V) Symbol tcycle tAS tAH tDSW tDHW TCLKL TCLKH tCSS tCSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Chip Select Setup Time (for D7 input) Chip Select Hold Time (for D0 input) Rise Time Fall Time Min 58.8 10 5 30 30 29.4 29.4 30 29.4 Typ Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns D/C tAS tAH tCSH tcycle CS tCSS tCLKL tCLKH SCK(D6) tF tDSW tR tDHW SDA(D7) Valid Data CS SCK(D6) SDA(D7) D7 D6 D5 D4 D3 D2 D1 D0 Figure 16 - 4-wires Serial Interface Timing Characteristics (P/S = L, C68/80 = L) SSD1805 Series Rev 1.1 P 45/52 Jun 2004 Solomon Systech 13 APPLICATION EXAMPLES DISPLAY PANEL SIZE 132 X 68 COM34 COM35 : : : : : : : COM66 COM67 COM0 COM1 : : : : : : : COM32 COM33 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 : : : : : : : : : : : : : : : : : : : SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 Row remapped command [command: C0H] ROW67 .......ROW34 COL0 ................................................................................................. COL131 ROW33 ................ROW0 SSD1805 IC (DIE FACE UP) C1 C2 ,where VDD & VCI = 2.775V; VDDIO = 2.775V; C1 = 1uF ~2uF; C2 = 2.2uF ~ 4.7uF. Logic pin connections not specified above: Pins connected to VDD: IRS; M/ S ; CLS; E( RD ); CS2; /HPM; Pins connected to VSS: P/ S ; C68/( 80 ); VSS1; VLREF; D0~D5; R/W ( WR ); TEST0; Pin connected to VOUT: VHREF; Pins connected to Either VDD or VSS depending on configuration: C0; C1; B0; B1; Software initialization (For 68 MUX application) E2 //Software reset 2F //Turn on regulated charge-pump and divider 86 //Set 5X booster configuration 24 //Set internal resistor gain to 24Hex 81 //Set contrast level to 20Hex 20 // A2 //Set normal bias ratio as 1/9 bias AF //Set Display On D / C CS RES SCK SDA VDDIO VDD VCI VSS VOUT Figure 17 - Application Example I (4-wires SPI mode) Solomon Systech Jun 2004 P 46/52 Rev 1.1 SSD1805 Series DISPLAY PANEL SIZE 132 X 68 COM34 COM35 : : : : : : : COM66 COM67 COM0 COM1 : : : : : : : COM32 COM33 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 : : : : : : : : : : : : : : : : : : : SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 Row remapped command [command: C0H] ROW67 .......ROW34 COL0 ................................................................................................. COL131 ROW33 ................ROW0 SSD1805 IC (DIE FACE UP) C1 C2 D / C R/W ( WR )CS RES E( RD ) D0 ... D7 VDDIO VDD VCI VSS VOUT ,where VDD & VCI = 2.775V; VDDIO = 2.775V; C1 = 1uF ~2uF; C2 = 2.2uF ~ 4.7uF. Logic pin connections not specified above: Pins connected to VDD: IRS; M/ S ; CLS; P/ S ; C68/( 80 ); CS2; /HPM; Pins connected to VSS: VSS1; VLREF; TEST0; Pin connected to VOUT: VHREF; Pins connected to Either VDD or VSS depending on configuration: C0; C1; B0; B1; Figure 18 - Application Example II (6800 PPI mode) SSD1805 Series Rev 1.1 P 47/52 Jun 2004 Solomon Systech Figure 19 - Applications notes for VDD/VDDIO connection 2.775V 2.775V 2.775V CLS M/S /CS1 /RES D/C R/W E D0~D7 VDDIO VDD VCI VOUT VHREF MCU SSD1805 VSS VSS1 VLREF Normal Application 1.8V 2.775V or 1.8V CLS M/S /CS1 /RES D/C R/W E D0~D7 1.8V 2.775V VDDIO VDD VCI VOUT VHREF MCU SSD1805 VSS VSS1 VLREF Low Voltage MCU Solomon Systech Jun 2004 P 48/52 Rev 1.1 SSD1805 Series 14 PACKAGE INFORMATION 14.1 DIE TRAY DIMENSIONS Spec W1 W2 H K E Px Py X Y Z N mm 50.70 0.2 45.50 0.2 4.05 0.2 N/A N/A 14.19 0.1 2.48 0.1 11.26 + 0.1 1.41 + 0.1 0.68 0.05 51 (mil) (1996) (1791) (160) (559) (98) (443) (58) (27) SSD1805 Series Rev 1.1 P 49/52 Jun 2004 Solomon Systech 14.2 TAB DRAWING Figure 20 - SSD1805TR1 TAB Drawing (Copper view) Solomon Systech Jun 2004 P 50/52 Rev 1.1 SSD1805 Series 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 21 - SSD1805TR1 TAB Drawing (Detail view & pin assignment) SSD1805 Series Rev 1.1 P 51/52 Jun 2004 Solomon Systech Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part http://www.solomon-systech.com Solomon Systech Jun 2004 P 52/52 Rev 1.1 SSD1805 Series |
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